1. Field of the Invention
The present invention relates to a frequency divider, and more particularly, to a frequency divider for RF transceivers, which utilizes general-purpose flip-flops.
2. Description of the Prior Art
A local oscillator (LO) path in a communication system provides the mixing tone to up convert low frequency modulated signals in a transmitter, and to down convert received signals so that they may be demodulated. Currently, as die sizes of integrated circuits are getting smaller, on-channel LO frequencies interacting with and corrupt received and transmitted radio frequency (RF) signals has become a serious problem.
In direct conversion receivers, wherein direct conversion implies that in the receiver the LO frequency is equal to the received RF frequency, interactions between the LO signal and the RF signal due to coupling through the substrate of the chip can lead to DC offsets, which corrupt data in modulation schemes such as EDGE or GSM containing information at DC.
One way to avoid this phenomenon is to divide the LO frequency by three and then to double or quadruple it. This guarantees that neither the LO nor any of its harmonics correspond to the received RF frequency.
R. Magoon and A. Molnar in “RF Local Oscillator Path for GSM Direct Conversion Transceiver with True 50% Duty Cycle Divide by Three and Active Third Harmonic Cancellation, page 23˜26, 2002 IEEE Radio Frequency Integrated Circuit Symposium” disclosed such an RF local oscillator path. Please refer to FIG. 1. FIG. 1 shows a diagram of an LO path 10 using a UHF (Ultra-High Frequency) VCO (Voltage-Controlled Oscillator) with fc=1350 MHz according to the prior art. The LO path 10 comprises a VCO 12 for generating an oscillating signal with a central frequency fc=1350 MHz; a divide-by-three frequency divider 14 electrically connected to the VCO 12, for dividing the frequency of the oscillating signal by three to generate a 450 MHz signal; a first frequency doubler 16 electrically connected to the frequency divider 14, for multiplying the frequency of the signal generated by the frequency divider 14 by two to generate a 900 MHz signal, which can be used as an LO signal in a GSM system; and a second frequency doubler 18 electrically connected to the first frequency doubler 16, for multiplying the frequency of the signal generated by the first frequency doubler 16 by two to generate a 1800 MHz signal, which can be used as an LO signal in a DCS or a PCS system.
Now please refer to FIG. 2. FIG. 2 shows a divide-by-three frequency divider 20 according to prior art. In the prior art LO path 10 shown in FIG. 1, the frequency divider 20 in FIG. 2 is used as the frequency divider 14. The frequency divider 20 comprises a first, a second, and a third phase switchable D flip-flops 22, 24, 26. Each phase switchable D flip-flop has a data input node D, a clock input node clk, a first output node Q, and a second output node Qbar for outputting a logic signal complementary to a logic signal outputted at the first output node Q, as an ordinary general-purpose D flip-flop does. In addition to those, each phase switchable D flip-flop in FIG. 2 further has a phase-switching input node θ. By dynamically driving the phase-switching input node θ of the flip-flop, a signal at the first output node Q can be made to transition on either a rising edge or a falling edge of a signal inputted at the clock input node clk.
Please refer to FIG. 3. FIG. 3 shows a circuit diagram of a phase switchable D flip-flop according to prior art, used as phase switchable D flip-flops 22, 24, 26 in FIG. 2. The phase switchable D flip-flop in FIG. 3 is composed of a plurality of ECL (Emitter Coupled Logic) transistors and a plurality of resistors. All the signals are inputted and outputted differentially.
In FIG. 2, the data input node D1 of the first flip-flop 22 is electrically connected to the second output node Qbar3 of the third flip-flop 26, and the phase-switching input node θ1 of the first flip-flop 22 is electrically connected to the first output node Q2 of the second flip-flop 24. The data input node D2 of the second flip-flop 24 is electrically connected to the first output node Q1 of the first flip-flop 22, and the phase-switching input node θ2 of the second flip-flop 24 is electrically connected to the second output node Qbar3 of the third flip-flop 26. The data input node D3 of the third flip-flop 26 is electrically connected to the first output node Q2 of the second flip-flop 24, and the phase-switching input node θ3 of the third flip-flop 26 is electrically connected to the second output node Qbar1 of the first flip-flop 22. Finally, all the clock input nodes clk1, clk2, clk3 of the first, the second, and the third flip-flops 22, 24, 26 are electrically connected to an input signal in, which is the signal with the central frequency fc=1350 MHz generated by the VCO 12 in FIG. 1.
Now please refer to FIG. 4. FIG. 4 shows a time sequence of signals at the nodes shown in FIG. 2. Under the configuration in FIG. 2, signals at the first output nodes Q1, Q2, Q3 of the flip-flops 22, 24, 26 have frequencies one-third a frequency of the input signal in at the clock input nodes clk1, clk2, clk3, wherein the signal at the first output node Q1 leads the signal at the first output node Q2 by a 60° phase difference, and the signal at the first output node Q2 leads the signal at the first output node Q3 by a 60° phase difference.
The divide-by-three frequency divider in FIG. 2 utilizing the phase-switching D flip-flop in FIG. 3 serves the purpose of the LO path in FIG. 1 well. However, since the phase-switching D flip-flop in FIG. 3 is far more complex than a general-purpose flip-flop and requires more circuitry to implement, and a consequently larger chip area, an LO path with such a frequency divider tends to have increased costs of manufacture.